1. Field of the Invention
The present invention relates to a semiconductor device, particularly, to a MIS (Metal Insulator Semiconductor) type FET (Field Effect Transistor) device having a silicide film formed in a part of the source/drain diffusion layers.
2. Description of the Related Art
In a semiconductor device comprising a transistor such as an MIS (including MOS (Metal Oxide Semiconductor)) type FET, so called a border-less contact technology may be adopted. The technology does not provide an allowance between the transistor region in which a transistor is formed and the contact region in which a contact is formed in order to avoid an inconvenience caused by a deviation of a mask pattern.
FIGS. 9 to 12 collectively show the conventional manufacturing process of a transistor by using the border-less contact. As shown in FIG. 9, an element separating insulating film 102 and a well diffusion layer 103 are formed in the surface region of semiconductor substrate 101, followed by forming a gate insulating film 112, a gate electrode 113 and a first side wall insulating film 115. Then, a second diffusion region 122 is formed in a surface region of the well diffusion layer 103.
Then, as shown in FIG. 10, a second side wall insulating film 116 and a first diffusion region 121 are formed. Then, silicide films 114a, 114b are formed.
Then, as shown in FIG. 11, an interlayer insulating film 131 is formed, followed by forming a contact hole 134 in the interlayer insulating film 131 by an anisotropic etching such as RIE (Reactive Ion Etching) using a mask having an opening in the position corresponding to the contact hole 134.
Then, as shown in FIG. 12, the contact hole 134 is filled with a tungsten film 132 with the laminate structure (not shown) interposed therebetween.
In the lithography process, a mask position may be deviated, causing the opening of the mask for the contact hole 134 to sit on the element separating insulating film 102. Therefore, as shown in FIG. 11, a trench 141 may be formed in the element separating insulating film 102 in forming the contact hole 134.
FIG. 13 shows in a magnified fashion the region surrounded by a circle of the solid line in FIG. 12. As shown in FIG. 13, if the trench 141 is formed, the contact 132a, 132b are also formed in the trench 141 when filling the contact hole 134. If the trench 141 is deep enough to reach the junction between the first diffusion region 121 and the well diffusion layer 103, a short circuit is brought about in the junction.
Also, even when the trench 141 is not seriously deep, the trench 141 may reach the side surface of the first diffusion region 121, as shown in FIG. 13, causing a silicide layer 142 to form. As a result, a leak current flowing through the silicide layer 142 increases between the first diffusion region 121 and the well diffusion layer 103.
It also should be noted that the first diffusion region 121 is rendered shallower as the semiconductor device shrinks, which makes the distance between the bottom of the silicide film 114b and the junction between the first diffusion region 121 and the well diffusion layer 103 decrease. Even if the silicide layer 142 is not formed, the junction leak current from the silicide film 114b increases.
It should be noted that due to, e.g. the etching conditions, these problems are not generated uniformly, which lowers the yield of the semiconductor device.
Further, if the gate length is rendered 100 nm or less, simply lowering the accelerating energy in the ion implantation process to form the second diffusion layer 122 greatly rises the sheet resistance of this region, which makes the driving capability of the transistor deteriorate. The dose, i.e. the number of impurity atoms to be implanted, can be increased to avoid the problem. However, this solution scarcely increases the amount of the impurity atoms that are actually activated within silicon, and does not overcome the problem. In addition, the deeper the second diffusion region 122 reaches, the more device characteristics deteriorate. Particularly, the short channel effect occurs.
The formation of the trench 141 may be avoided by controlling, for example, the etching time for forming the contact hole 134. However, it is difficult to avoid the problem for each element separating insulating film 102, due to the controllability of the etching.
It is also conceivable to form a liner material layer such that the liner material layer extends from above the element separating insulating film 102 onto the silicide layer 114a. However, it is impossible to ensure a sufficiently large etching selectivity between the materials generally used for the insulating films 131, 102 and the liner material to overcome. the problem.
Incidentally, in a conventional NMOS device, the aforementioned problems in a PMOS are also generated.